A 384G Output NonZeros/J Graph Convolutional Neural Network Accelerator
Author:
Affiliation:
1. Department of Convergence IT Engineering, Pohang University of Science and Technology, Pohang, South Korea
2. Department of Electronic and Electrical Engineering, Pohang University of Science and Technology, Pohang, South Korea
Funder
National Research Foundation
Korea Ministry of Science and ICT
IC Design Education Center
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8920/9900496/09815108.pdf?arnumber=9815108
Reference19 articles.
1. 9.5 A 6K-MAC Feature-Map-Sparsity-Aware Neural Processing Unit in 5nm Flagship Mobile SoC
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4. A 7.3 M output non-zeros/J sparse matrix-matrix multiplication accelerator using memory reconfiguration in 40 nm;pal;Proc Symp VLSI Technol,2019
5. MatRaptor: A Sparse-Sparse Matrix Multiplication Accelerator Based on Row-Wise Product
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