An 11-15.8GHz Class-D DCO with -117.5 dBc/Hz Phase Noise at 1 MHz Offset in 22nm FDSOI CMOS Technology
Author:
Affiliation:
1. GlobalFoundries,China
2. GlobalFoundries,Germany
3. GlobalFoundries,USA
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10288583/10288635/10288829.pdf?arnumber=10288829
Reference10 articles.
1. A 19.5-GHz 28-nm Class-C CMOS VCO, With a Reasonably Rigorous Result on 1/f Noise Upconversion Caused by Short-Channel Effects
2. A Low Power Fully-Integrated 76-81 GHz ADPLL for Automotive Radar Applications with 150 MHz/us FMCW Chirp Rate and -95dBc/Hz Phase Noise at 1 MHz Offset in FDSOI
3. A High-Performance Low Power Compact Wideband X-band DCO Based on Transformer Coupled Feedback
4. A filtering technique to lower LC oscillator phase noise
5. The impact of device type and sizing on phase noise mechanisms
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