A Low Power Fully-Integrated 76-81 GHz ADPLL for Automotive Radar Applications with 150 MHz/us FMCW Chirp Rate and -95dBc/Hz Phase Noise at 1 MHz Offset in FDSOI
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/8700146/8701725/08701826.pdf?arnumber=8701826
Cited by 8 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A high-linear PLL-based FMCW frequency synthesizer with 42-kHz rms FM error and 1.2-GHz chirp bandwidth;IEICE Electronics Express;2024-05-25
2. An Ultra-Wideband Reference Frequency Chirp Generator Utilizing Fractional Frequency Divider With High Linearity;IEEE Open Journal of Circuits and Systems;2024
3. A 16 GHz Duty-Cycled Charge Pump PLL-Based Chirp Synthesizer;Synthesis Lectures on Engineering, Science, and Technology;2024
4. A 10 GHz Sub-Sampling PLL Chirp Synthesizer Using a Charge-Integrating DAC;Synthesis Lectures on Engineering, Science, and Technology;2024
5. Introduction;Synthesis Lectures on Engineering, Science, and Technology;2024
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