2nm Node: Benchmarking FinFET vs Nano-Slab Transistor Architectures for Artificial Intelligence and Next Gen Smart Mobile Devices-Reference-Cited by-同舟云学术

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2nm Node: Benchmarking FinFET vs Nano-Slab Transistor Architectures for Artificial Intelligence and Next Gen Smart Mobile Devices

Published:2019-06 Issue: Volume: Page:
ISSN:
Container-title:2019 Symposium on VLSI Technology
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Author:

Song S.C.,Colombeau B.,Bauer M.,Moroz V.,Lin X-W.,Asenov P.,Sherlekar D.,Choi M.,Huang J.,Cheng B.,Chidambaram C.,Natarajan S.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8766306/8776475/08776478.pdf?arnumber=8776478

Cited by 18 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design Technology Co-Optimization for Gate-All-Around Nanosheet Transistors Considering Source/Drain Confinement and Post- Gate Single Diffusion Break;IEEE Transactions on Electron Devices;2024-07

2. An Advanced Packaging Figure of Merit (AP-FoM) for Benchmarking of Heterogeneous Integration Technologies;2024 IEEE 74th Electronic Components and Technology Conference (ECTC);2024-05-28

3. Gate-All-Around SRAM: Performance Investigation and Optimization Towards Vccmin Scaling;2024 IEEE International Memory Workshop (IMW);2024-05-12

4. Effect of Process-Induced Variations on Analog Performance of Silicon based Nanosheet Transistor;Silicon;2023-02-27

5. ECONOMIC AND TECHNICAL ADVANTAGES OF REDUCTION METHOD FOR PARAMETRIC DEVIATIONS DUE TO TECHNOLOGICAL IMPERFECTION IN COMPARATOR;ALTERNATIVE;2023

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