ECONOMIC AND TECHNICAL ADVANTAGES OF REDUCTION METHOD FOR PARAMETRIC DEVIATIONS DUE TO TECHNOLOGICAL IMPERFECTION IN COMPARATOR

Abstract

Nowadays devices sizes in integrated circuits (IC) have reached up to 2nm [1]. In this case, the parameters characterizing the reliability and speed of the circuits, even in the case of small deviations of the technological processes, may violate to an unacceptable extent their characteristic values [2]. Such deviations may be caused by random technological imperfections. The modeling of the deviations described above is done by Monte-Carlo analysis [3]. Parametric deviations due to technological imperfections were considered and minimized on the example of the comparator [4], because one of the main disadvantages of this scheme is the dependence of its characteristic values on deviations caused by the technological process imperfections. The proposed comparator scheme makes it possible to minimize the effect of deviations caused by the imperfection of the technological process without significant surface changes on the semiconductor crystal. By using the scheme of the proposed comparator, it was possible to reduce the hysteresis deviations from 31.11% to 5.21%. The proposed comparator scheme requires an additional 19% space against the existing scheme.