RLPlace: Deep RL Guided Heuristics for Detailed Placement Optimization
Author:
Affiliation:
1. University of California,San Diego
2. Nvidia Corporation
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9774496/9774497/09774684.pdf?arnumber=9774684
Reference16 articles.
1. VLSI placement parameter optimization using deep reinforcement learning
2. Routability-Driven Macro Placement with Embedded CNN-Based Prediction Model
3. GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning
4. Reinforcement Learning for Placement Optimization
5. Placement in integrated circuits using cyclic reinforcement learning and simulated annealing;vashisht;ArXiv,0
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