Graph Neural Network-based Delay-Fault Localization for Monolithic 3D ICs
Author:
Affiliation:
1. Duke University,Department of Electrical and Computer Engineering,Durham,NC,USA,27708
Funder
National Science Foundation
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9774496/9774497/09774513.pdf?arnumber=9774513
Reference24 articles.
1. 3D technologies for analog/RF applications
2. NodeRank: Observation-Point Insertion for Fault Localization in Monolithic 3D ICs∗
3. Power Supply Noise-Aware Scan Test Pattern Reshaping for At-Speed Delay Fault Testing of Monolithic 3D ICs *
4. X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector
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1. Machine Learning for Test, Diagnosis, Post-Silicon Validation and Yield Optimization;2022 IEEE European Test Symposium (ETS);2022-05-23
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