Body resistance model for Partially Depleted SOI device: charge-based approach, extraction and Verilog-A implementation-Reference-Cited by-同舟云学术

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Body resistance model for Partially Depleted SOI device: charge-based approach, extraction and Verilog-A implementation

Published:2023-09-27 Issue: Volume: Page:
ISSN:
Container-title:2023 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)
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Author:

Martinie Sébastien¹,Vaysset Adrien¹,Mourrier Yannick²,Scheer Patrick²,Rozeau Olivier¹

Affiliation:

1. Univ. Grenoble Alpes, CEA, Leti,Grenoble,France,F-38000

2. STMicroelectronics,Crolles,France

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10319472/10319477/10319516.pdf?arnumber=10319516

Reference7 articles.

1. PD-SOI CMOS and SiGe BiCMOS Technologies for 5G and 6G communications;chevalier;Solid-State Electronics,2009

2. Analytical approximation for the MOSFET surface potential

3. PSP-SOI: An advanced surface potential based compact model of partially depleted SOI MOSFETs for circuit simulations

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