Author:
Asgari Bahar,Hadidi Ramyad,Kim Hyesoon
Cited by
11 articles.
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1. ROMA: A Reconfigurable On-chip Memory Architecture for Multi-core Accelerators;2023 IEEE International Conference on High Performance Computing & Communications, Data Science & Systems, Smart City & Dependability in Sensor, Cloud & Big Data Systems & Application (HPCC/DSS/SmartCity/DependSys);2023-12-17
2. LCP: A Low-Communication Parallelization Method for Fast Neural Network Inference for IoT;2023 Congress in Computer Science, Computer Engineering, & Applied Computing (CSCE);2023-07-24
3. Context-Aware Task Handling in Resource-Constrained Robots with Virtualization;2023 IEEE International Conference on Edge Computing and Communications (EDGE);2023-07
4. Reducing Inference Latency with Concurrent Architectures for Image Recognition at Edge;2023 IEEE International Conference on Edge Computing and Communications (EDGE);2023-07
5. Creating Robust Deep Neural Networks with Coded Distributed Computing for IoT;2023 IEEE International Conference on Edge Computing and Communications (EDGE);2023-07