Characteristic Analysis of a Multi-chip Embedded Interposer Carrier using a Wafer-Level Fan-Out Process-Reference-Cited by-同舟云学术

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Characteristic Analysis of a Multi-chip Embedded Interposer Carrier using a Wafer-Level Fan-Out Process

Published:2022-05-11 Issue: Volume: Page:
ISSN:
Container-title:2022 International Conference on Electronics Packaging (ICEP)
language:
Short-container-title:

Author:

Lee Ching Kuan¹,Liu Wen-Hung¹,Chang Shu-Yi¹,Cheng Ren-Shin¹,Lin Yu-Min¹,Ding Hsiang-En¹,Chiu Wei-Lan¹,Chang Tao-Chih¹,Lee Chia-Hsin²,Lee Chang-Chun³

Affiliation:

1. Industrial Technology Research Institute (ITRI),Electronics and Optoelectronics Research Laboratories,Hsinchu,Taiwan

2. National Yang Ming Chiao Tung University (NYCU),Hsinchu,Taiwan

3. National Tsing Hua University,Department of Power Mechanical Engineering,Hsinchu,Taiwan

Funder

Ministry of Economic Affairs

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9795348/9795361/09795583.pdf?arnumber=9795583

Reference4 articles.

1. A novel multi-chip stacking technology development using a flip-chip embedded interposer carrier integrated in fan-out wafer-level packaging

2. An innovative embedded interposer carrier for high density interconnection

3. Recent Advances and Trends in Advanced Packaging

4. Advances in Embedded and Fan‐Out Wafer‐Level Packaging Technologies

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