Monolithic 3D Integration of FeFET, Hybrid CMOS Logic and Analog RRAM Array for Energy-Efficient Reconfigurable Computing-In-Memory Architecture
Author:
Affiliation:
1. Tsinghua University,School of Integrated Circuits, ICFC, BNRist,Beijing,China,100084
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10185199/10185158/10185221.pdf?arnumber=10185221
Reference6 articles.
1. A compute-in-memory chip based on resistive random-access memory
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