Fully Integrated 3-D Stackable CNTFET/RRAM 1T1R Array as BEOL Buffer Macro for Monolithic 3-D Integration With Analog RRAM-Based Computing-in-Memory-Reference-Cited by-同舟云学术

Fully Integrated 3-D Stackable CNTFET/RRAM 1T1R Array as BEOL Buffer Macro for Monolithic 3-D Integration With Analog RRAM-Based Computing-in-Memory

Published:2024-05 Issue:5 Volume:71 Page:3343-3350
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Zhang Yibei¹,Li Yijun¹,Tang Jianshi¹^ORCID,Gao Lei²,Gao Ningfei²,Xu Haitao²,An Ran¹,Qin Qi¹^ORCID,Liu Zhengwu¹,Wu Dong¹,Gao Bin¹^ORCID,Qian He¹,Wu Huaqiang¹^ORCID

Affiliation:

1. School of Integrated Circuits, ICFC, BNRist, Tsinghua University, Beijing, China

2. Beijing Institute of Carbon-based Integrated Circuits, Beijing, China

Funder

STI 2030-Major Projects

National Natural Science Foundation of China

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx7/16/10508280/10479585.pdf?arnumber=10479585

Reference28 articles.

1. 33.2 A Fully Integrated Analog ReRAM Based 78.4TOPS/W Compute-In-Memory Chip with Fully Parallel MAC Computing

2. Coming Up N3XT, After 2D Scaling of Si CMOS

3. Monolithic 3D Integration of FeFET, Hybrid CMOS Logic and Analog RRAM Array for Energy-Efficient Reconfigurable Computing-In-Memory Architecture

4. A Hybrid Computing-In-Memory Architecture by Monolithic 3D Integration of BEOL CNT/IGZO-based CFET Logic and Analog RRAM

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Monolithic 3-D-Based Nonvolatile Associative Processor for High-Performance Energy-Efficient Computations;IEEE Journal on Exploratory Solid-State Computational Devices and Circuits;2024