Comprehensive Investigation of Back Gate Biasing on Performance of Line TFETs
Author:
Affiliation:
1. Sardar Vallabhbhai National Institute of Technology,Department of Electronics Engineering,Surat,India
2. University of Pisa,Department of Information Engineering,Italy
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10183871/10183917/10183969.pdf?arnumber=10183969
Reference8 articles.
1. Fabrication and Analysis of a ${\rm Si}/{\rm Si}_{0.55}{\rm Ge}_{0.45}$ Heterojunction Line Tunnel FET
2. On the Static and Dynamic Behavior of the Germanium Electron-Hole Bilayer Tunnel FET
3. 0.5 V Supply Voltage Operation of In0.65Ga0.35As/GaAs0.4Sb0.6Tunnel FET
4. Impact of Gate–Source Overlap on the Device/Circuit Analog Performance of Line TFETs
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