Dataflow-Aware PIM-Enabled Manycore Architecture for Deep Learning Workloads
Author:
Affiliation:
1. Washington State University Pullman,WA
2. University of Wisconsin Madison,Madison,WI
Funder
National Science Foundation
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10546498/10546499/10546730.pdf?arnumber=10546730
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1. Enabling interposer-based disintegration of multi-core processors;Kannan;MICRO,2015
2. SWAP: A Server-Scale Communication-Aware Chiplet-Based Manycore PIM Accelerator
3. Kite: A Family of Heteroge neous Interposer Topologies Enabled via Accurate Interconnect Modeling;Bharadwaj;DAC,2020
4. AccuReD: High Accuracy Training of CNNs on ReRAM/GPU Heterogeneous 3-D Architecture
5. Monolithic 3D: an alternative to advanced CMOS scaling, technology perspectives and associated design methodology challenges
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