SRAM Design Issues and Effective Panacea at Different CMOS Technology Nodes
Author:
Affiliation:
1. Bharati Vidyapeeth’s College of Engineering,Paschim Vihar, New Delhi,India
2. HMRITM,New Delhi,India
3. GLA University,Mathura,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9770852/9770880/09770897.pdf?arnumber=9770897
Reference30 articles.
1. Compact Analytical Model to Extract Write Static Noise Margin (WSNM) for SRAM Cell at 45-nm and 65-nm Nodes
2. Digital Integrated Circuit Lecture;dasgupta,0
3. CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies
4. Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems
5. Static Noise Margin Analysis of modified 6T SRAM cell during read operation;rehman;International Journal on Recent Trends in Engineering & Technology,2013
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