PIC-RAM: Process-Invariant Capacitive Multiplier Based Analog In Memory Computing in 6T SRAM
Author:
Affiliation:
1. Indian Institute of Technology,Department of Electrical Engineering,Gandhinagar,India
Funder
Ministry of Electronics and Information Technology
Semiconductor Research Corporation
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10136870/10136706/10137338.pdf?arnumber=10137338
Reference16 articles.
1. CAP-RAM: A Charge-Domain In-Memory Computing 6T-SRAM for Accurate and Precision-Programmable CNN Inference
2. In-memory Multibit Multiplication Based on Bitline Shifting;zhang;IEEE Transactions on Circuits and Systems II Express Briefs,2021
3. A Charge-Sharing based 8T SRAM In-Memory Computing for Edge DNN Acceleration
4. ±CIM SRAM for Signed In-Memory Broad-Purpose Computing From DSP to Neural Processing
5. 17.1 a 0.6 v 1.5 ghz 84mb sram design in 14nm finfet cmos technology;karl;ISSCC Digest,2015
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1. FP-ATM: A Flexible Floating Point NOR Adder Tree Macro for In-Memory Computing;2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID);2024-01-06
2. Resonant Compute-In-Memory (rCIM) 10T SRAM Macro for Boolean Logic;2023 IEEE 41st International Conference on Computer Design (ICCD);2023-11-06
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