1. Multiplier Design Addressing Area-Delay Trade-offs by using DSP and Logic resources on FPGAs;2024 IEEE 35th International Conference on Application-specific Systems, Architectures and Processors (ASAP);2024-07-24
2. Small Logic-based Multipliers with Incomplete Sub-Multipliers for FPGAs;2024 IEEE 31st Symposium on Computer Arithmetic (ARITH);2024-06-10
3. High-efficiency Compressor Trees for Latest AMD FPGAs;ACM Transactions on Reconfigurable Technology and Systems;2024-04-30
4. Binary Neural Networks in FPGAs: Architectures, Tool Flows and Hardware Comparisons;Sensors;2023-11-17
5. Sums of Weighted Bits;Application-Specific Arithmetic;2023-08-23