Securing a RISC-V architecture: A dynamic approach-Reference-Cited by-同舟云学术

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Securing a RISC-V architecture: A dynamic approach

Published:2023-04 Issue: Volume: Page:
ISSN:
Container-title:2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)
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Author:

Pillement S.¹,Real M. Méndez¹,Pottier J.¹,Nieddu T.²,Gal B. Le²,Faucou S.³,Béchennec J.L.³,Briday M.³,Girbal S.⁴,Rhun J. Le⁴,Gilles O.⁴,Pérez D. Gracia⁴,Sintzoff A.⁵,Coulon J.R.⁵

Affiliation:

1. Nantes Université,CNRS,Nantes,France,F-44000

2. Univ. Bordeaux,Bordeaux INP, CNRS, IMS,Talence,France,F-33400

3. Nantes Université,CNRS, LS2N,Nantes,France,F-44000

4. Thales Research & Technology,Palaiseau,France

5. Thales DIS,Meyreuil,France

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10136870/10136706/10136972.pdf?arnumber=10136972

Reference19 articles.

1. The Dover inherently secure processor

2. Risc v and security: How, when and why;handschuh;Cryptographic Hardware and Embedded Systems-CHES,0

3. Context-Sensitive Decoding: On-Demand Microcode Customization for Security and Energy Management

4. Reconfigurable RISC-V Secure Processor And SoC Integration

5. The Origin of Intel's Micro-Ops

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