Equivalence Checking of System-Level and SPICE-Level Models of Static Nonlinear Circuits
Author:
Affiliation:
1. Institute of Computer Science, University of Bremen,Bremen,Germany,28359
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10136870/10136706/10137179.pdf?arnumber=10137179
Reference26 articles.
1. Approaches to Formal Verification of Analog Circuits
2. A formal approach to nonlinear analog circuit verification
3. Advanced methods for equivalence checking of analog circuits with strong nonlinearities
4. Formal Verification for Nonlinear Analog Systems: Approaches to Model and Equivalence Checking
5. Equivalence Checking Methods for Analog Circuits Using Continuous Reachable Sets
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