The impact of high-k dielectrics on the performance of Schottky barrier source/drain (SBSD) ultra-thin body (UTB) SOI MOSFET

Abstract

The impact of high-k dielectrics on the performance of Schottky barrier source/drain (SBSD) ultra-thin body (UTB) SOI is investigated in this paper. With the dielectric constants increasing, the on-state currents of SBSD UTB SOI MOSFET decrease, which suggests that the fringing induced barrier lowering (FIBL) is not the major mechanism for the variation of Schottky barrier height. This phenomenon can be understood in terms of the fringing induced barrier shielding (FIBS). It is also shown that the influence of high-k dielectrics on the performance is quite different in the cases that source/drain and gate electrode have an offset or overlap. For the device with an overlap， the structure with a low-k interfacial layer between high-k gate dielectric and substrate is quite effective in suppressing the degradation of drive current due to FIBS. However, for the device with an offset, the combination of high-k dielectric spacer with stack gate can significantly improve the on-state current. This fact can be explained in terms of the refraction of lines of electric force from gate electrode at interfaces of two materials with different dielectric constants. These lines of electric force with refraction can concentrate at the source region, thus lowering the barrier heights and improving the drive currents. Besides, it is shown that on-state current has a local maximum in the case that source/drain and gate electrode has an offset. The structure parameters can be optimized to improve the drive current.