A two-dimensional threshold voltage analytical model for metal-gate/high-k/SiO2/Si stacked MOSFETs
Author:
Publisher
IOP Publishing
Subject
General Physics and Astronomy
Reference19 articles.
1. Threshold voltage analytical model for strained Si SOI MOSFET with high-k dielectric
2. The impact of high-k dielectrics on the performance of Schottky barrier source/drain (SBSD) ultra-thin body (UTB) SOI MOSFET
3. High dielectric constant gate oxides for metal oxide Si transistors
4. Threshold voltage model for MOSFETs with high-k gate dielectrics
Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Performance Analysis of Gate-Stack Nanoscaled Recessed-S/D SOI-MOSFET for Analog Applications;Lecture Notes in Electrical Engineering;2021-12-14
2. LOGIC-BASED SWITCHING ADAPTIVE CONTROL FOR CHAOTIC SYSTEM WITH UNKNOWN PARAMETERS1;Control and Intelligent Systems;2015
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