Characteristics of latch-up current of dose rate effect by laser simulation

Abstract

Due to the parasitic PNPN structure, the complementary metal oxide semiconductor (CMOS) integrated circuit may be affected by the latch-up effect, and the latching induced by the transient high dose rate Gamma ray has unique characteristics. In order to explore the complex physical mechanism of the latch-up by transient dose rate effect, in this paper we select the pulsed laser with 1064 nm wavelength as an radiation source to simulate the gamma ray radiation environment, select bulk silicon CMOS deserializer FIN1218MTDX, and use transient dose rate effect laser simulation experiments to explore its latch-up threshold and latch-up current characteristics. The test obtains that the dose rate latch-up threshold optical power density of the device at 3.3 V operating voltage is (8.5 ± 1.2) × 10⁴ W/cm², a latch-up voltage of the device is 2.8 V, only the device latches when the supply voltage is greater than 2.8 V. At the same time, it is found that under the working voltages of 3.3 V and 3.6 V and the optical power density between 1.9 × 10⁶ W/cm² and 1.6 × 10⁷ W/cm², the latch-up current significantly decreases, the latch-up current " window phenomenon” appears. Based on the equivalent circuit model, the multi-path latching mechanism is used to construct the HSPICE model. The mechanism of the transient dose rate latching characteristics exposed by the laser test is analyzed by circuit-level simulation. The results show that the latch-up current and the latch-up voltage are related to its own latch structure when the device is latched. The phenomenon of latch-up current window in laser test is due to the multi-path latch mechanism, which will be in the specific circuit structure, and causing the multiple latch-up paths of the device to be switched. The reason of the latch-up path is switched is that the different holding voltages and trigger conditions between the latch-up paths, distributed resistance in the circuit reduces the voltage of latch-up path, so that the holding voltage of the latch-up path cannot be satisfied and the latch-up path is released. At the same time the other latch-up path is latched.