Author:
Bi Jin-Shun ,Hai Chao-He ,Han Zheng-Sheng ,
Abstract
A large signal equivalent circuit model of SOI LDMOS is proposed. Power gain and power-added efficiency of n-type LDMOS are modeled. Deep sub-micron SOI LDMOS was fabricated and measured. We investigated the dependence of SOI LDMOS power characteristics on channel length, single gate finger width, supply voltage and working frequency. Power gain and power-added efficiency are increased by 44％ and 9％, respectively, with channel length reduction from 0.5 μm to 0.35 μm. When single gate finger width is increased from 20 μm to 40 μm, power gain and power-added efficiency of 600 μm /0.5 μm device are decreased by 23％ and 9.3％, respectively. Power-gain and power-added efficiency are increased by 13％ and 5.5％, respectively, with supply voltage increased from 3 V to 5 V. When the working frequency is increased from 2.5 GHz to 3.0 GHz, power gain and power added efficiency of LDMOS are decreased by 15％ and 4.5％, respectively.
Publisher
Acta Physica Sinica, Chinese Physical Society and Institute of Physics, Chinese Academy of Sciences
Subject
General Physics and Astronomy
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