High-performance Sub-5nm Monolayer Tin Sulfide (SnS) Field-effect Transistors: a First principles Study

Abstract

Presently Si-based field-effect transistors (FET) are approaching their physical limit and challenging Moore's law for their short-channel effect, and further scaling their gate length down to the sub-10 nm region is becoming extremely difficult. Two-dimensional (2D) layered semiconductors with atom-scale uniform thicknesses and absence of dangling bonds on the interface are considered as potential channel materials to support further miniaturization and integrated electronics. Wu F, et al. (2022 Nature 603 259) have successfully fabricated a FET with gate lengths below 1 nm using atomically thin molybdenum disulfide with exceptional device performance. This breakthrough has greatly encouraged further theoretical predictions regarding the performance of 2D devices. Additionally, 2D SnS exhibits high carrier mobility, anisotropic electronic properties, and stabilized in ambient condition conducive to advanced applications in 2D semiconductor technology. Herein, we explore the quantum transport properties of sub-5 nm monolayer (ML) SnS FET using first-principles quantum transport simulation. Considering the anisotropic electronic SnS, the double-gated-two-probe device model is constructed along the armchair and zigzag directions of ML SnS. After test five kinds of doping concentrations, a doping concentration of 5×10¹³ cm^-2 is the best one for SnS FET. We also used the underlap (UL) with range of 0, 2, and 4 nm to improve the device performance. On-state current (<i>I</i>_on) is an important parameter for evaluating the transition speed of a logic device. A higher <i>I</i>_on of a device can help to increase the switching speed of high-performance (HP) servers. The main conclusions are as follows.<br>1) <i>I</i>_on of the n-type 2 nm (UL=4 armchair), 3 nm (UL=2), 4 nm (UL=3), 5 nm (UL=0) and the p-type 1 nm (UL=2 zigzag), 2 nm (UL=2 zigzag), 3 nm (UL=2,4 zigzag), 4 nm (UL=2,4 zigzag), and 5 nm (UL=0, armchair/zigzag) gate-length devices can meet the standards for HP applications for the next decade in the International Technology Roadmap for semiconductors (ITRS, 2013 version).<br>2) <i>I</i>_on of the n-type device along the armchair direction (31-2369μA/μm) are larger than that in the zigzag direction (4.04-1943μA/μm), while p-type along the zigzag direction (545-4119μA/μm) are larger than that in the armchair direction (0.7-924μA/μm). Therefore, the p-type ML GeSe MOSFETs have a predominantly anisotropic current.<br>3) <i>I</i>_on of the p-type 3 nm gate-length (UL=0) device along the zigzag direction has the highest valued 4119 μA/μm is 2.93 times larger than that in the same gate-length UL=2 (1407μA/μm). Hence, an overlong UL will weaken the performance of the device because the gate of the device cannot well control the UL region. Thus, a suitable length of UL for FET is very important.<br>4) Remarkably, <i>I</i>_on of the p-type devices (zigzag), even at a 1 nm gate-length, can fulfill the requirements of HP applications for the next decade in the ITRS, with a value as high as 1934 μA/μm. To our knowledge, this is the best-performing device material reported at 1 nm gate length.<br>5) Subthreshold swing (SS) evaluates the control ability of the gate in the subthreshold region. The better the gate control, the smaller SS the device has. The limit of SS for traditional FETs is 60 mV/dec (at room temperature). Values of SS for ML SnS FET alone zigzag direction are less than those along the armchair direction because the leakage current is influenced by the effective mass.