Establishment of analytical model for electrostatic discharge gate-to-source capacitance of power metal-oxide-semiconductor field-effect transistor

Abstract

In the actual human body model (HBM) test, it is found that the electrostatic discharge (ESD) test results of various power metal-oxide-semiconductor field-effect transistor (MOSFET) devices show asymmetry between forward withstand voltage and reverse withstand voltage, while the ESD process does not distinguish between positive direction and negative direction. Large differences between forward and reverse withstand voltages are unacceptable for power MOSFETs or as ESD protection devices. The problem of its causing device failure is particularly pronounced. In this work, by establishing the analytical model of gate-to-source capacitance of SGT-MOSFET, VUMOSFET and VDMOS under the forward and reverse voltages, we comparatively analyze the reasons for the asymmetry of the forward and reverse withstand voltages and their different ratios of the three kinds of power MOSFETs, which provides a theoretical basis for testing the device’s ESD and the analyzing their reliability. It is found that the ESD forward and reverse withstand voltage asymmetry phenomena of different power MOSFET structures are related to the variation of gate-to-source capacitance, caused by the reverse-type layer. When a forward voltage is applied across the gate and source, the device gate-to-source capacitance consists of the oxide layer capacitance around the gate in parallel; when a reverse voltage is applied, the gate-to-source capacitance consists of the virtual gate-to-drain capacitance in series with the inverse layer capacitance and then in parallel with the other oxide layer capacitance around the gate. This results in a decrease of the gate-to-source capacitance at the reverse voltage, making the device reverse withstand voltage greater than the forward withstand voltage. The difference in the ratio of ESD reverse withstand voltage to forward withstand voltage among different devices is related to the change of the capacitance of the inverse layer in the gate-to-source capacitor under reverse voltage caused by the difference in device structure.