Impact of Deep Cryogenic Temperatures on High-k Stacked Dual Gate Junctionless MOSFET Performance: Analog and RF analysis

Author:

Ghosh Rittik1,Nelapati Rajeev Pankaj1

Affiliation:

1. Vellore Institute of Technology

Abstract

Abstract This article presents the reliability analysis of a High-k stacked Dual Gate Junction-less MOSFET at Deep Cryogenic Temperatures (as low as 50 Kelvin) in terms of dc, analog and RF stability performance metrics. Furthermore, the dc and analog figure of merits in the presence polarized interface trap charge densities has been analyzed at sub-ambient temperatures. The steep ON-OFF switching and the sub-threshold slope profile shows heavy reliance on temperature variations and confirm that the transistor electrostatics improve at lower temperatures. The study reveals the compatibility of the device to perform at cryogenic temperatures and can be integrated with CMOS technology for quantum computations.

Publisher

Research Square Platform LLC

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