A novel Self-Biased pMOS Clamped Deep Trench CSTBT with Enhanced Short-Circuit Capability

Abstract

In this work, a novel deep trench CSTBT (DT-CSTBT) features emitter trench and the P-layer is proposed and investigated by simulation. The self-biased pMOS, comprising an emitter trench, N-CS layer, P-layer, and P-well, demonstrates an excellent clamping effect potential. The proposed DT-CSTBT suppresses the saturation current under the clamping effect, resulting in a 23.5% expansion of the short-circuit safe operating area (SCSOA). It ensures the better reliability of the gate due to the high electric field away from the gate. Furthermore, the tradeoff relationship between on-state voltage (V_on) and turn-off loss (E_off) of the new structure is also improved by 23.2% compared with the conventional CSTBT.