A low power injection-locked CDR using 28 nm FDSOI technology for burst-mode applications

Author:

Mao Yuqing1,Charlon Yoann1,Jacquemod Gilles1,Leduc Yves1

Affiliation:

1. Université Côte d’Azur

Abstract

Abstract In this paper, a low-power Injection-Locked Clock and Data Recovery (ILCDR) using 28 nm FDSOI technology is presented. The back-gate auto-biasing of UTBB-FDSOI transistors allows us to create a QRO (Quadrature Ring Oscillator) reducing both size and power consumption. By injecting a digital signal into this circuit, we realize an Injection-Locked Oscillator (ILO) with low jitter. Thanks to the good performance of this oscillator, we can propose a low power ILCDR with low jitter and fast locking time for burst-mode applications. The main novelty consists in the implementation of a complementary QRO based on back-gate control using FDSOI technology in order to realize a simple and efficient ILCDR circuit. With a Pseudo-Random Binary Sequence (27 PRBS) at 868Mbps, the recovered clock jitter is 18.5 ps (1.6%UIp-p) and the recovered data jitter is 18.7 ps (1.6%UIp-p). With a 0.6 V power supply, the power consumption is 4.67 mA (2.8 mW). The estimated Chip size is around 6600 µm².

Publisher

Research Square Platform LLC

Reference22 articles.

1. Architectures for multi-gigabit wire-linked clock and data recovery;Hsieh M;IEEE Circuits and Systems Magazine,2008

2. Challenges in the design high-speed clock and data recovery circuits;Razavi B;IEEE Communications Magazine,2002

3. Wei, Z., Leduc, Y., de Foucauld, E., & Jacquemod, G. (2017). “Novel Building Blocks for PLL Using Complementary Logic in 28nm UTBB-FDSOI Technology”, NewCAS, Strasbourg, France, pp. 121–124,

4. Mao, Y., Charlon, Y., Debieu, F., Wei, Z., Leduc, Y., & Jacquemod, G. (2021). Ultra low power injection-locked ring oscillator architecture using FDSOI technology. France: AVIC, Bordeaux

5. Wang, Y., Zhang, L., Han, W., Li, X., Lai, F., & Liu, X. (2016). "A low-jitter PLL with new cross-coupled VCO delay cell for SerDes CDR in 55-nm CMOS technology," 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), pp. 1434–1436, doi: 10.1109/ICSICT.2016.7998761

Cited by 1 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. New design of an ultra low power CDR architecture using FDSOI 28 nm technology;2023 21st IEEE Interregional NEWCAS Conference (NEWCAS);2023-06-26

同舟云学术

1.学者识别学者识别

2.学术分析学术分析

3.人才评估人才评估

"同舟云学术"是以全球学者为主线,采集、加工和组织学术论文而形成的新型学术文献查询和分析系统,可以对全球学者进行文献检索和人才价值评估。用户可以通过关注某些学科领域的顶尖人物而持续追踪该领域的学科进展和研究前沿。经过近期的数据扩容,当前同舟云学术共收录了国内外主流学术期刊6万余种,收集的期刊论文及会议论文总量共计约1.5亿篇,并以每天添加12000余篇中外论文的速度递增。我们也可以为用户提供个性化、定制化的学者数据。欢迎来电咨询!咨询电话:010-8811{复制后删除}0370

www.globalauthorid.com

TOP

Copyright © 2019-2024 北京同舟云网络信息技术有限公司
京公网安备11010802033243号  京ICP备18003416号-3