High Speed and Area Efficient Address Generator architecture for WiMAX Deinterleaver

Abstract

Abstract In this paper, A VLSI Implementation of High Speed and Area Efficient Address Generation architecture for deinterleaver in WiMAX applications. The emphasis of the design is to reduce the complexity and high speed to optimize the design. This design for WLAN IEEE 802.16e (WiMAX) Standard has designed an efficient hardware resource implemented in FPGA and ASIC environments. A simple architecture was designed with better performance than an existing one. The multiplier-less architecture which satisfies the area efficacy, clock latency, and delay. The Modified QPSK, 16QAM, and 64 QAM standard systems with standard code rate was designed. This approach provides a significant improvement in hardware resources.