Easily-Extendable Line Decoder with Low Transistor Count and High Power-Delay Performance

Abstract

Abstract An easily-extendable 12-transistor 2-4 line decoder core is presented for the random-access memory interface such as translation lookaside buffer and the first level data cache in this brief. The core idea is to design the line decoder based on the truth table straightforwardly without assistant of the basic gate circuits. The 3-8 line decoder and 4-16 line decoder can be constructed with three and seven of the proposed 2-4 decoder core, respectively, resulting in a low transistor count and high power-delay performance. Simulation results shows that the proposed decoder topologies have the minimum area overhand compared with the state of the art in 65nm CMOS process. Meanwhile, the delay of the 2-4 line decoder is reduced to 120.7 ps, 57.5 ps, and 37 ps at 0.8 V, 1 V and 1.2 V, respectively, resulting in a better PNPD performance. Besides, the PNPD of the proposed 2-4 and 4-16 topology is optimized by 1.7%, and 10.94% compared with that of the HP topologies, while the PNPD of the 3-8 line decoder is optimized by 32.59% compared with that of the predecoder structure at a 1V supply voltage.