Author:
Turi M.A.,Delgado-Frias J.G.
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Cited by
13 articles.
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1. High-performance and low-power decoder circuits for SRAMs using mixed-logic scheme;Integration;2024-09
2. Simultaneous Many-Row Activation in Off-the-Shelf DRAM Chips: Experimental Characterization and Analysis;2024 54th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN);2024-06-24
3. Functionally-Complete Boolean Logic in Real DRAM Chips: Experimental Characterization and Analysis;2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA);2024-03-02
4. Comparative Analysis of Decoders using Static & Dynamic CMOS Logic;2023 International Conference on Advances in Electronics, Communication, Computing and Intelligent Information Systems (ICAECIS);2023-04-19
5. A Low-Cost Reduced-Latency DRAM Architecture With Dynamic Reconfiguration of Row Decoder;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-01