1. Ramji Gupta, A., & Pandey, R. K. (2018). Baghel. Efficient design of chaos based 4 bit true random number generator on FPGA, International Journal of Engineering & Technology, 7 (3) 1783–1785 Website: www.sciencepubco.com/index.php/IJET 10.14419/ijet.v7i3.16586.
2. Gupta, R., & Pandey, A. (2018). R. K. Baghel. Comparative Analysis of True Random Number Generator, 1st International Conference on New Frontiers in Engineering, Science & Technology,New Delhi, India, January 8–12.
3. FPGA implementation of chaos-based high‐speed true random number generator,Research Article,Wiley;Gupta R;Int J Numer Model,2019
4. A process and temperature tolerant oscillator-based true random number generator;Amaki T;IEICE Trans Fundamentals,2014
5. Brederlow, R., Prakash, R., Paulus, C., & Thewes, R. (2006). A low-power true random number generator using random telegraph noise of single oxide-traps, IEEE International Solid State Circuits Conference -Digest of Technical Papers 1666–1675.