DRAMSys: A Flexible DRAM Subsystem Design Space Exploration Framework

Author:

Jung Matthias1,Weis Christian1,Wehn Norbert1

Affiliation:

1. University of Kaiserslautern

Publisher

Information Processing Society of Japan

Subject

Electrical and Electronic Engineering,Computer Science Applications

Reference53 articles.

1. [1] Wulf, W.A. and McKee, S.A.: Hitting the memory wall: implications of the obvious, SIGARCH Comput. Archit. News, (online), DOI: 10.1145/216585.216588 (1995).

2. [2] Jedec Solid State Technology Association: DDR3 SDRAM (JESD 79-3) (2012).

3. [3] Jedec Solid State Technology Association: DDR4 SDRAM (JESD 79-4) (2012).

4. [4] Krueger, J., Donofrio, D., Shalf, J., Mohiyuddin, M., Williams, S., Oliker, L. and Pfreundt, F.-J.: Hardware/software co-design for energy-efficient seismic modeling, High Performance Computing, Networking, Storage and Analysis (SC), 2011 International Conference for, pp.1-12 (2011).

5. [5] Jedec Solid State Technology Association: Wide I/O Single Data Rate (JESD 229) (2011).

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