Energy-efficient High-level Synthesis for HDR Architectures-Reference-Cited by-同舟云学术

Energy-efficient High-level Synthesis for HDR Architectures

Published:2012 Issue:0 Volume:5 Page:106-117
ISSN:1882-6687
Container-title:IPSJ Transactions on System LSI Design Methodology
language:en
Short-container-title:IPSJ Transactions on System LSI Design Methodology

Author:

Abe Shin-ya,Yanagisawa Masao,Togawa Nozomu

Publisher

Information Processing Society of Japan

Subject

Electrical and Electronic Engineering,Computer Science Applications

Link

https://www.jstage.jst.go.jp/article/ipsjtsldm/5/0/5_106/_pdf

Reference18 articles.

1. Architecture and Synthesis for On-Chip Multicycle Communication

2. [3] Cong, J., Fan, Y. and Xu, J.: Simultaneous resource binding and interconnection optimization based on a distributed register-file microarchitecture, ACM Trans. Design Automation of Electronic Systems, Vol.14, No.3, pp.1-31 (2009).

3. [4] International technology roadmap for semiconductors (ITRS) (2005), available from <http://www/itrs/net/>.

4. [5] Jeon, J., Kim, D., Shin, D. and Choi, K.: High-level synthesis under multi-cycle interconnect delay, Proc. ASP-DAC '01, pp.662-667 (2001).

5. [6] Johnson, M. and Roy, K.: Datapath scheduling with multiple supply voltages and level converters, ACM Trans. Design Automation of Electronic Systems, Vol.2, No.3, pp.227-248 (1997).

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Bitwidth-Aware High-Level Synthesis Algorithm Using Operation Chainings for Tiled-DR Architectures;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2017

2. Interconnection-Delay and Clock-Skew Estimate Modelings for Floorplan-Driven High-Level Synthesis Targeting FPGA Designs;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2016

3. A Multi-Scenario High-Level Synthesis Algorithm for Variation-Tolerant Floorplan-Driven Design;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2016

4. Multi-scenario high-level synthesis for dynamic delay variation and its evaluation on FPGA platforms;IEICE Electronics Express;2016

5. A Floorplan-Driven High-Level Synthesis Algorithm for Multiplexer Reduction Targeting FPGA Designs;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2015