Current Pass Optimized Symmetric Pass Gate Adiabatic Logic for Cryptographic Circuits-Reference-Cited by-同舟云学术

Current Pass Optimized Symmetric Pass Gate Adiabatic Logic for Cryptographic Circuits

Published:2019 Issue:0 Volume:12 Page:50-52
ISSN:1882-6687
Container-title:IPSJ Transactions on System LSI Design Methodology
language:en
Short-container-title:IPSJ Transactions on System LSI Design Methodology

Author:

Koyasu Hiroki¹,Takahashi Yasuhiro¹

Affiliation:

1. Graduate School of Natural Science and Technology, Gifu University

Publisher

Information Processing Society of Japan

Subject

Electrical and Electronic Engineering,Computer Science Applications

Link

https://www.jstage.jst.go.jp/article/ipsjtsldm/12/0/12_50/_pdf

Reference5 articles.

1. [1] Tiri, K., Akmal, M. and Verbauwhede, I.: A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power, Proc. ESSCIRC 2002, pp.403-406 (2002).

2. [2] Monteiro, C., Takahashi, Y. and Sekine, T.: Charge-sharing symmetric adiabatic logic in countermeasure against power analysis attacks at cell level, Microelectronics J., Vol.44, No.6, pp.496-503 (2013).

3. [3] Avital, M., Dagan, H., Levi, I., Keren, O. and Fish, A.: DPA-secured quasi-adiabatic logic (SQAL) for low-power passive RFID tags employing S-boxes, IEEE Trans. Circuits and Syst. I., Vol.62, No.1, pp.149-156 (2015).

4. [4] Kumar, S.D., Thapliyal, H., Mohammad, A. and Perumalla, K.S.: Design exploration of a symmetric pass gate adiabatic logic for energy-efficient and secure hardware, Integr. VLSI J., Vol.58, pp.369-377 (2017).

5. [5] Liu, C.-H., Huang, N.-F. and Lee, C.-Y.: Computation of AB² multiplier in GF(2^m) using an efficient low-complexity cellular architecture, IEICE Trans. Fundamentals, Vol.E-83A, No.12, pp.2657-2663 (2000).

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