Voltage controlled delay line for digital signal

Abstract

This paper describes dual delay locked loop architecture with a mixed mode phase tuning method. The circuit accomplishes low jitter, unlimited phase shift in a large operating range, and accurate phase alignment with high resolution for relatively low input clock frequency. The architecture employs two DLL loops. The first one is digital and is used for generating coarsely spaced clock pulses, while the second is analog and is intended for accurate and precise fine phase shifting. Simulations show that this circuit has 2?r radians phase shift capability, and can resolve 25ps phase error at input clock frequency of 1MHz, using 1.2^m double-metal double-poly CMOS technology.