Extraction of source/drain resistivity parameters optimized for double-gate FinFETs-Reference-Cited by-同舟云学术

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Extraction of source/drain resistivity parameters optimized for double-gate FinFETs

Published:2015-01-29 Issue:4S Volume:54 Page:04DC06
ISSN:0021-4922
Container-title:Japanese Journal of Applied Physics
language:
Short-container-title:Jpn. J. Appl. Phys.

Author:

Yoon Jun-Sik,Jeong Eui-Young,Lee Sang-Hyun,Kim Ye-Ram,Hong Jae-Ho,Lee Jeong-Soo,Jeong Yoon-Ha

Publisher

IOP Publishing

Subject

General Physics and Astronomy,Physics and Astronomy (miscellaneous),General Engineering

Link

https://iopscience.iop.org/article/10.7567/JJAP.54.04DC06/pdf

Reference30 articles.

1. A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors

2. A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications

3. A 16nm FinFET CMOS technology for mobile SoC and computing applications

4. 13.2 A 14nm FinFET 128Mb 6T SRAM with VMIN-enhancement techniques for low-power applications

5. Extension and source/drain design for high-performance finFET devices

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Optimization of nanosheet number and width of multi-stacked nanosheet FETs for sub-7-nm node system on chip applications;Japanese Journal of Applied Physics;2019-03-20

2. Contact resistances in trigate and FinFET devices in a non-equilibrium Green's functions approach;Journal of Applied Physics;2016-02-28

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