The influence of post-etch InGaAs fin profile on electrical performance-Reference-Cited by-同舟云学术

The influence of post-etch InGaAs fin profile on electrical performance

Published:2014-01-01 Issue:4S Volume:53 Page:04EC20
ISSN:0021-4922
Container-title:Japanese Journal of Applied Physics
language:
Short-container-title:Jpn. J. Appl. Phys.

Author:

Ivanov Tsvetan,Pourghaderi Mohammad Ali,Lin Dennis,Yu Jen-Kan,Tan Samantha,Kimura Yoshie,Hellin David,Geypen Jeffrey,Bender Hugo,Vertommen Johan,Kamarthy Gowri,Collaert Nadine,Marks Jef,Vahedi Vahid,Arghavani Reza,Thean Aaron

Publisher

IOP Publishing

Subject

General Physics and Astronomy,Physics and Astronomy (miscellaneous),General Engineering

Reference30 articles.

1. Ultimate Scaling of CMOS Logic Devices with Ge and III–V Materials

2. Epitaxy of III–V based channels on Si and transistor integration for 12-10nm node CMOS

3. First experimental demonstration of 100 nm inversion-mode InGaAs FinFET through damage-free sidewall etching

4. Non-planar, multi-gate InGaAs quantum well field effect transistors with high-K gate dielectric and ultra-scaled gate-to-drain/gate-to-source separation for low power logic applications

5. Advanced high-K gate dielectric for high-performance short-channel In0.7Ga0.3As quantum well field effect transistors on silicon substrate for low power logic applications

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