Short-Channel Junctionless Nanowire Transistors-Reference-Cited by-同舟云学术

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Short-Channel Junctionless Nanowire Transistors

Published:2010-09-24 Issue: Volume: Page:
ISSN:
Container-title:Extended Abstracts of the 2010 International Conference on Solid State Devices and Materials
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Author:

Lee C. W.,Ferain I.,Kranti A.,Akhavan N. Dehdashti,Razavi P.,Yan R.,Yu R.,O'Neill B.,Blake A.,White M.,Kelleher A. M.,McCarthy B.,Gheorghe S.,Murphy R.,Colinge J. P.

Publisher

The Japan Society of Applied Physics

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Effect of Temperature, Doping and Gate Material Engineering on Tri-Gate SOI nFinFET Performance Through TCAD Simulation;Transactions on Electrical and Electronic Materials;2024-05-11

2. A Junctionless Single Transistor Neuron With Vertically Stacked Multiple Nanowires for Highly Scalable Neuromorphic Hardware;IEEE Transactions on Electron Devices;2022-06

3. Impact of Gaussian Doping on SRAM Cell Stability in 14nm Junctionless FinFET Technology;Silicon;2021-10-11

4. An Optimized Ge Pocket SOI JLT with Efforts to Improve the Self-Heating Effect: Doping & Materials Perspective;Silicon;2019-11-25

5. Effect of Geometric Parameters on the Performance of P-Type Junctionless Lateral Gate Transistors;PLoS ONE;2014-04-17

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