Capacitorless one-transistor dynamic random-access memory based on asymmetric double-gate Ge/GaAs-heterojunction tunneling field-effect transistor with n-doped boosting layer and drain-underlap structure-Reference-Cited by-同舟云学术

Capacitorless one-transistor dynamic random-access memory based on asymmetric double-gate Ge/GaAs-heterojunction tunneling field-effect transistor with n-doped boosting layer and drain-underlap structure

Published:2018-02-19 Issue:4S Volume:57 Page:04FG03
ISSN:0021-4922
Container-title:Japanese Journal of Applied Physics
language:
Short-container-title:Jpn. J. Appl. Phys.

Author:

Yoon Young Jun,Seo Jae Hwa,Man Kang In

Publisher

IOP Publishing

Subject

General Physics and Astronomy,Physics and Astronomy (miscellaneous),General Engineering

Link

http://stacks.iop.org/1347-4065/57/i=4S/a=04FG03/pdf

Reference32 articles.

1. A capacitor-less 1T-DRAM cell

2. A capacitorless double-gate DRAM cell

3. A capacitorless double gate DRAM technology for sub-100-nm embedded and stand-alone memory applications

4. A capacitorless 1T-DRAM technology using gate-induced drain-leakage (GIDL) current for low-power and high-speed embedded memory

5. Novel Vertical SOI-Based 1T-DRAM With Trench Body Structure

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