Lowering data retention voltage in static random access memory array by post fabrication self-improvement of cell stability by multiple stress application-Reference-Cited by-同舟云学术

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Lowering data retention voltage in static random access memory array by post fabrication self-improvement of cell stability by multiple stress application

Published:2018-03-05 Issue:4S Volume:57 Page:04FD08
ISSN:0021-4922
Container-title:Japanese Journal of Applied Physics
language:
Short-container-title:Jpn. J. Appl. Phys.

Author:

Mizutani Tomoko,Takeuchi Kiyoshi,Saraya Takuya,Kobayashi Masaharu,Hiramoto Toshiro

Publisher

IOP Publishing

Subject

General Physics and Astronomy,Physics and Astronomy (miscellaneous),General Engineering

Link

http://stacks.iop.org/1347-4065/57/i=4S/a=04FD08/pdf

Reference32 articles.

1. The impact of intrinsic device fluctuations on CMOS SRAM cell stability

2. Re-Examination of Impact of Intrinsic Dopant Fluctuations on Static RAM (SRAM) Static Noise Margin

3. Stable SRAM cell design for the 32 nm node and beyond

4. Fluctuation limits & amp; scaling opportunities for CMOS SRAM cells

5. A 256kb Sub-threshold SRAM in 65nm CMOS

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