Single‐phase phase locked loop with DC offset and noise rejection for photovoltaic inverters-Reference-Cited by-同舟云学术

Single‐phase phase locked loop with DC offset and noise rejection for photovoltaic inverters

Published:2014-09 Issue:9 Volume:7 Page:2288-2299
ISSN:1755-4543
Container-title:IET Power Electronics
language:en
Short-container-title:IET Power Electronics

Author:

Lubura Slobodan¹,Šoja Milomir¹,Lale Srd‐an¹,Ikić Marko¹

Affiliation:

1. Faculty of Electrical EngineeringUniversity of East Sarajevo, RSEast SarajevoBosnia and Herzegovina

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-pel.2013.0413

Reference20 articles.

1. Operation of a phase locked loop system under distorted utility conditions

2. Stationary-frame generalized integrators for current control of active power filters with zero steady-state error for current harmonics of concern under unbalanced and distorted operating conditions

3. 2001 36th IAS Annual Meeting. Conf. Record of the 2001 IEEE Industry Applications Conf. 2001 L.N. Arruda S.M. Silva B.J.C. Filho PLL structures for utility connected systems 2655 2660

4. 2000 IEE Proc. Electric Power Applications S.‐K. Chung Phase‐locked loop for grid‐connected three‐phase power conversion systems 213 219

5. 2006 37th IEEE Power Electronics Specialists Conf. 2006. PESC ′06 M. Ciobotaru R. Teodorescu F. Blaabjerg A new single‐phase PLL structure based on second order generalized integrator 1 6

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