Optimal loop filter design of a DC immunity single-phase PLL based single delay operator
Author:
Funder
Deanship of Research, Jordan University of Science and Technology
Publisher
Springer Science and Business Media LLC
Link
https://link.springer.com/content/pdf/10.1007/s40435-024-01454-z.pdf
Reference33 articles.
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2. Kulkarni A, John V (2017) Design of a fast response time single-phase PLL with DC offset rejection capability. Electr Power Syst Res 145:35–43. https://doi.org/10.1016/j.epsr.2016.12.023
3. Ardalan P, Rasekh N, Khaneghah MZ et al (2022) A modified SOGI-FLL algorithm with DC-offset rejection improvement for single-phase inverter applications. Int J Dynam Control 10:2020–2033. https://doi.org/10.1007/s40435-022-00932-6
4. Lubura S, Šoja M, Lale SA, Ikić M (2014) Single-phase phase locked loop with DC offset and noise rejection for photovoltaic inverters. IET Power Electron 7(9):2288–2299. https://doi.org/10.1049/iet-pel.2013.0413
5. Hwang SH, Liu L, Li H, Kim JM (2012) DC offset error compensation for synchronous reference frame PLL in single-phase grid-connected converters. IEEE Trans Power Electron 27(8):3467–3471. https://doi.org/10.1109/TPEL.2012.2190425
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