Development of fault‐tolerant MLI topology
Author:
Affiliation:
1. Department of Electrical EngineeringNIT RaipurRaipurIndia
2. Department of Electrical EngineeringIIT BombayBombayIndia
Funder
Science and Engineering Research Board
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-pel.2017.0683
Reference24 articles.
1. Reliability improvement of transistor clamped H‐bridge‐based cascaded multilevel inverter
2. BakerR.H. andBannisterL.H.: ‘Electric power converter’. US Patent 3 867 643 February 1975
3. Hybrid topology of symmetrical multilevel inverter using less number of devices
4. An Industry-Based Survey of Reliability in Power Electronic Converters
5. Analysis and Design of Active NPC (ANPC) Inverters for Fault-Tolerant Operation of High-Power Electrical Drives
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