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Effect of glitches against masked AES S-box implementation and countermeasure

  • Published:2009-03-01 Issue:1 Volume:3 Page:34-44
  • ISSN:1751-8709
  • Container-title:IET Information Security
  • language:en
  • Short-container-title:

Author:

Alam M.,Mukhopadhyay D.,Ghosh S.,Gupta I.S.,Chowdhury D.R.,Mohan M.J.

Publisher

Institution of Engineering and Technology (IET)

Subject

Computer Networks and Communications,Information Systems,Software

Cited by 11 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. SM4 Chaotic Masking Scheme Against Power Analysis Based on FPGA;International Journal of Bifurcation and Chaos;2022-06-30

2. Guarding Machine Learning Hardware Against Physical Side-channel Attacks;ACM Journal on Emerging Technologies in Computing Systems;2022-04-28

3. Formal Evaluation and Construction of Glitch-resistant Masked Functions;2021 IEEE International Symposium on Hardware Oriented Security and Trust (HOST);2021-12-12

4. A novel SCA-resilience flip-flop design utilizing the current mode logic based on the three-independent-gate field effect transistors;IEICE Electronics Express;2021-08-25

5. A Comprehensive Evaluation of Integrated Circuits Side-Channel Resilience Utilizing Three-Independent-Gate Silicon NanoWire Field Effect Transistors based Current Mode Logic;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2021
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