Analysis of trap‐assisted tunnelling in asymmetrical underlap 3D‐cylindrical GAA‐TFET based on hetero‐spacer engineering for improved device reliability-Reference-Cited by-同舟云学术

Analysis of trap‐assisted tunnelling in asymmetrical underlap 3D‐cylindrical GAA‐TFET based on hetero‐spacer engineering for improved device reliability

Published:2017-12 Issue:12 Volume:12 Page:982-986
ISSN:1750-0443
Container-title:Micro & Nano Letters
language:en
Short-container-title:Micro & Nano Letters

Author:

Beohar Ankur¹,Yadav Nandakishor¹,Vishvakarma Santosh Kumar¹

Affiliation:

1. Discipline of Electrical EngineeringIndian Institute of TechnologyIndore453552Madhya PradeshIndia

Funder

Council of Scientific and Industrial Research, India

Publisher

Institution of Engineering and Technology (IET)

Subject

Condensed Matter Physics,General Materials Science,Biomedical Engineering,Bioengineering

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/mnl.2017.0311

Reference30 articles.

1. Tunnel field-effect transistors as energy-efficient electronic switches

2. Silicon Nanowire Tunnel FETs: Low-Temperature Operation and Influence of High- $k$ Gate Dielectric

3. Effect of Drain Doping Profile on Double-Gate Tunnel Field-Effect Transistor and its Influence on Device RF Performance

4. Design and analysis of Si-based arch-shaped gate-all-around (GAA) tunneling field-effect transistor (TFET)

5. Hetero-Gate-Dielectric Tunneling Field-Effect Transistors

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