Implementation of a Boolean function with a double-gate vertical TFET (DGVTFET) using numerical simulations

Author:

Mathew Ribu,Beohar Ankur,Ghosh Jyotirmoy,Sarkar Pallabi,Upadhyay Abhishek Kumar

Funder

SERB TARE GRANT, Govt. of India

Publisher

Springer Science and Business Media LLC

Reference37 articles.

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3. Mano, M.M., Michael, C.: Digital design: with an introduction to the Verilog HDL. Pearson, London (2013)

4. Joshi, M., Dutt, A., Tiwari, S., Nigam, P., Beohar, A., Mathew, R.: Impact of channel splitting on gate all around tunnel field effect transistor (GAA-TFET). Devices Integr. Circuit (DevIC) 2021, 1–5 (2021)

5. Beohar, A., Vishvakarma, S.K.: Performance enhancement of asymmetrical underlap 3D-cylindrical GAA-TFET with low spacer width. IET Micro Nano Lett. 11(8), 443–445 (2016)

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