Error‐compensated time integrator in 28‐nm CMOS technology
Author:
Affiliation:
1. Nanjing University of Posts and TelecommunicationsNanjingPeople's Republic of China
2. Science and Technology on Analog Integrated Circuit LaboratoryChongqingPeople's Republic of China
Funder
National Natural Science Foundation of China
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1049/el.2020.1074
Reference5 articles.
1. Digital storage, addition and subtraction of time-mode variables
2. A 3.5–6.8-GHz Wide-Bandwidth DTC-Assisted Fractional-N All-Digital PLL With a MASH $\Delta \Sigma $ -TDC for Low In-Band Phase Noise
3. High‐precision differential time integrator based on time adder
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