A time latch for high speed time‐based ADCs
Author:
Affiliation:
1. Electrical and Computer Engineering Department Ohio State University Columbus Ohio USA
Funder
Intel Corporation
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1049/ell2.12535
Reference7 articles.
1. A 5 GS/s 150 mW 10 b SHA-Less Pipelined/SAR Hybrid ADC for Direct-Sampling Systems in 28 nm CMOS
2. A Time-Based Pipelined ADC Using Both Voltage and Time Domain Information
3. A 2-GS/s 8-bit Non-Interleaved Time-Domain Flash ADC Based on Remainder Number System in 65-nm CMOS
4. An 8-Bit 10-GS/s 16× Interpolation-Based Time-Domain ADC With <1.5-ps Uncalibrated Quantization Steps
5. Ziabakhsh S. Gagnon G. Roberts G.W.:An all‐digital high‐resolution programmable time‐difference amplifier based on time latch.IEEE International Symposium on Circuits and Systems (ISCAS) pp.1–5.IEEE Piscataway NJ(2018)
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