1. Rung, R.D., Momose, H., and Naoakubo, Y.: ‘Deep trench isolated CMOS devices’, IEDM Tech. Digest, 1982), p. 237–240
2. Fuse, G., Ogawa, H., Tateiwa, K., Nakao, I., Odanaka, S., Fukumoto, M., Iwasaki, H., and Ohzone, T.: ‘A practical trench isolation technology with a novel planarization process’, IEDM Tech. Digest, 1987), p. 732–735
3. Davari, B., Koburger, C., Furukawa, T., Taur, Y., Noble, W., Megdanis, A., Warnock, J., and Mauer, J.: ‘A variable-size shallow trench isolation (STI) technology with diffused sidewall doping for submicron CMOS’, IEDM Tech. Digest, 1988), p. 92–95